1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and its design method, and more particularly to the technique for fixing the well potential in a semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells.
2. Description of the Related Art
It is known that the element characteristics of the transistors formed in a semiconductor integrated circuit device, such as an IC or an LSI, are influenced by fluctuations in the well potential. To avoid such influence and stabilize the element characteristics of the transistors, it is necessary to stabilize (fix) the well potential.
In a semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells, each of the standard cells is provided with a power supply voltage terminal and a ground potential terminal. To fix the well potential, active regions called a P-sub region and an N-sub region are formed in the p-well region and n-well region, respectively. The p-well region is connected via the P-sub region to the ground potential terminal, thereby fixing the p-well region to the ground potential GND. The n-well region is connected via the N-sub region to the power supply voltage terminal, thereby fixing the n-well region to a power supply voltage VDD.
In standard cells, an interconnection for the power supply voltage VDD and an interconnection for the ground potential GND are provided to two sides facing each other in the direction in which the cells are arranged. In the semiconductor substrate under these interconnections, the p-well region and the n-well region are formed. In these well regions, semiconductor elements, including transistors, are formed so as to configure various circuits. In the p-well region and n-well region, the well potential fixing P-sub region and N-sub region are formed. The interconnection for the power supply voltage is electrically connected via a contact hole to the N-sub region and the interconnection for the ground potential is electrically connected via a contact hole to the P-sub region, thereby fixing the well potential.
To make use of the substrate bias effect of a MOS transistor positively, a standard cell may be used which has four terminals for the power supply voltage, ground potential, P-sub region, and N-sub regions (for example, referred to in Jpn. Pat. Appln. KOKAI Publication No. 2000-332118). The 4-terminal standard cell applies via independent lines the power supply voltage VDD, the ground potential GND, the potential VBN for fixing the n-well potential, and the potential VBP for fixing the p-well potential. In the 4-terminal standard cell, a line for applying the potential VBP for fixing the p-well potential and a line for applying the potential VBN for fixing the n-well potential are provided to two sides facing in the direction in which the cells are arranged. In the semiconductor substrate under these lines, the N-sub region and P-sub region are formed. The line for fixing the potential in the p-well region is electrically connected via a contact hole to the P-sub region and the line for fixing the potential in the n-well region is electrically connected via a contact hole to the N-sub region. Inside the lines, an interconnection for the power supply voltage VDD and an interconnection for the ground potential GND are arranged. The n-well region and p-well region are formed in the semiconductor substrate between the interconnections. In the n-well region and p-well region, semiconductor elements, including transistors, are formed so as to configure various circuits.
With the above configuration, however, the P-sub region and N-sub region for fixing the well potential and their interconnections lead to an increase in the cell area. To prevent the cell area from increasing, the sizes of semiconductor elements, including transistors, formed in the cell have to be reduced, resulting in a decrease in the driving capability. Particularly when the sub-regions and their interconnections are formed with the minimum line width according to design rules, the minimum distance or the like for the MOS transistors formed in the well region is limited or the step coating property is degraded. From these points of view, the cell area increases or the sizes of transistors must be reduced. In addition, contact with the densely arranged sub-regions necessitates complicated manufacturing processes. If there are a lot of such patterns, this results in a drop in the manufacturing yield.
With the miniaturization of semiconductor integrated circuit devices, the power supply voltage is getting lower and therefore the substrate current is getting smaller. Therefore, in a semiconductor integrated circuit device with a lowered power supply voltage, there is a possibility that the well potential can be fixed efficiently by minimizing a decrease in the driving capability due to an increase in the cell area or a reduction in the transistor size. This is because, when the power supply voltage comes close to 1V, a much potential difference needed for a forward current to flow through the p-n junction does not appear. Since not only the substrate current decreases due to the lowered power supply voltage, but also the source potential of the transistor is normally fixed, when the power supply voltage is about 1V, a fluctuation in the well potential caused by the coupling with the drain is less than 0.5V, half the power supply voltage. Therefore, there is almost no possibility that a breakdown will take place due to latch-up.
Naturally, when the substrate potential fluctuates at random, the driving capability of the transistor and the leakage current fluctuate according to the fluctuation of the potential. Therefore, to take measures against the fluctuations, the well potential has to be fixed.